Digital signal processing has been an enabling technology for high-speed telephony. Digital-Subscriber Lines (DSL) use highly-complex digital processing for line coding, data compression, and error correction. However, signals transmitted over the copper-pair telephone lines are analog signals. Conversion between the analog telephone signal and digital words is thus a critical piece of DSL systems.
Many kinds of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
Many interesting variations of these basic ADC types have been disclosed. See U.S. Pat. No. 5,459,465 by Kagey, U.S. Pat. No. 5,302,869 by Hosotani et al., and U.S. Pat. No. 5,436,629 by Mangseldorf.
FIG. 1 shows a prior-art pipelined ADC. See "A 2.5-v, 12-b 5-Msample/s Pipelined CMOS ADC", by Yu and Lee, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, December 1996, pp. 1854-61. Two stages 10, 10' are shown of the pipeline. Each stage 10, 10' converts its analog input to B digital bits. Sample-and-hold amplifier 12 receives the stage's analog input. ADC 14 receives the sampled analog voltage from amplifier 12 and converts it to B digital bits. These B digital bits are stored and also input to DAC 16.
DAC 16 re-converts the B digital bits back to an analog voltage that is applied to subtractor 18. Subtractor 18 then subtracts the re-converted voltage from DAC 16 from the sampled analog voltage from sample-and-hold amplifier 12, producing a difference or residue voltage. This residue voltage from subtractor 18 is then multiplied by 2.sup.B by amplifier 19. The output voltage from amplifier 19 is thus scaled back up in magnitude for input to the next successive stage 10'.
Each successive stage 10' generates another B digital bits of less significance than earlier stages 10. For example, first stage 10 produces the B most-significant-bits (MSBs), while second stage 10' produces the next B MSB's. The last stage (not shown) produces the final B bits, the least-significant-bits (LSBs). Simple, inexpensive ADCs and DAC's can be used for ADC 14 and DAC 16 when B is just 1 or 2 bits.
Pipelining the ADC's stages allows for higher throughput, since new samples can be taken and converted for every stage in the pipeline. A 10-stage pipeline can operate in parallel on 10 different analog samples at a time. While such an ADC is useful, many stages are needed when higher precision is needed. For example, when B=1 bit per stage, 16-bit precision requires 16 stages 10, 10'. Long pipelines increase delays or latencies until a conversion is completed. The serial pipeline structure increases power, area, and cost for the ADC.
What is desired is an Analog/Digital converter that uses a pipelined structure. A shorter pipeline is desired to reduce latency and cost. It is desired to reduce the pipeline depth by re-using ADC stages. It is desired to recirculate analog signals within a stage of a pipelined ADC. It is desired to use low-precision, low-cost ADC and DAC elements in a stage yet still achieve high overall precision with just a few stages.